Чему учат в школе

panchul — 16.08.2014 Сегодня я случайно увидел, чему учили в шестом классе моего старшего сына:







А еще сегодня я составил список из 100 пунктов, что должны знать студенты, которых мы четыре месяца учили по субботам на пару с Тимуром Палташевым из AMD в одном из местных университетов. Студенты в основном из Индии и Китая. Курс "Введение в SoC".

Причина, по которым я этим занимаюсь - я даю рекомендации по образовательным программам нашему менеджменту в Imagination Technologies, посему я должен знать, что за зверь является студент.

По этому списку я буду еще готовить список вопросов к экзамену. Предложения и замечания приветствуются.


Final exam topics:

General:

1. Relative sizes of the industries:

Electronic industry ~ $2T
Semiconductor / chip making industry ~ $300B
Electronic Design Automation industry ~ $8B
Semiconductor Intellectual Property (SIP) ~ $4B

2. RTL (Register Transfer Level) flow:

System architecture
Microarchitecture
Coding RTL
Simulation
Synthesis
Place and Route
Manufacturing

3. The difference between processor architecture and microarchitecture

Binary numbers:

4. Binary -> decimal conversion
5. Decimal -> binary conversion

6. Two's complement

Min negative, max positive
Method: invert the bits and add 1

7. Logical operations: and, or, xor
8. Arithmetic operations: +, -, *, /
9. Increasing bit width: sign-extension versus zero-extension

The concept of gate and combinational logic. Combinational building blocks. Combinational timing.

9. Gates: and, or, buffer, not, xor, nand, nor, xnor, multiple input gates
10. Multiplexers
11. [Encoders and decoders]
12. Adders: half-adder, full adder, ripple-carry adder
13. Shifters: logical and arithmetic shifters
14. Multipliers and dividers: combinational are not practical for many applications

Combinational timing:

15. Propagation delay and contamination delay
16. Critical (long) path and short path

Sequential logic, sequential building blocks and finite state machines (FSM):

17: SR Latch, how it stores the state
18. D Latch and D Flip-Flop: level-sensitive versus edge-sensitive. D Latch unwanted: bad for timing analysis.
19. D Flip-Flop reset: synchronous reset versus asynchronous reset
20. Sequential building block: counter
21. Sequential building block: shift register

22. The concept of state machine:

Inputs and outputs
Combinational logic and state register
Next state, current state

23. Moore FSM versus Mealy FSM
24. FSM State Transition Diagram
25. FSM Timing Diagram: Waveforms

Sequential logic timing:

26. The problem: Data should be stable when sampled in D Flip-Flop. Clock frequency should allow enough time for combinational logic to propagate.
27. Clock frequency and clock period
28. D Flip-flop setup time, hold time and aperture time
29. Propagation delay and contamination delay for clock-to-q
30. Dynamic discipline: minimum and maximum delay. Constraints and timing analysis.
31. Clock skew, worst case analysis
32. [Asynchronous inputs, metastability, synchronization using two D Flip-Flops]


Verilog

33. Hardware Description Languages (HDLs), their difference from programming languages
34. Verilog and VHDL. SystemVerilog
35. Simulation and synthesis. Synthesizable subset of Verilog, SystemVerilog and VHDL.
36. The concept of Verilog module, inputs and outputs
37. Main types: reg and wire in Verilog, reg/wire/logic in SystemVerilog. Variable width.
38. Module instantiation and hierarchy of modules
39. Combinational logic using simple “assign” statements
40. Bitwise logical operators: ~, &, |, ^. SystemVerilog: ~&, ~^, ~|
41. Reduction operators. Using xor (“^”) to compute parity.
42. Arithmetic operations: +, -, *, /, %
43. Arithmetic and logical shifts: <<, >>, <<<, >>>
44. [Conditional operator ?:]
45. [Bit manipulations: slices, concatenations and repetitions]
46. “always” block and its sensitivity list. always @*
47. Combinational “always” block (”always_comb” in SystemVerilog)
48. Control structures inside “always” blocks: “if”, “case” and “for”. Avoiding D latches.
49. Sequential “always” block (”always_ff” in SystemVerilog)
50. Blocking (“=”) and non-blocking (“<=”) assignments
51. Verilog race conditions. Importance of the correct methodology to avoid race conditions: blocking in combinational “always” block, non-blocking in sequential “always” blocks
52. Synthesizable code rule: a signal may be assigned only in one “always” block or “assign” statement
53. Coding Finite State Machines (FSMs): “always” block for the next state logic and “always” block for the state register
54. Testbenches: purpose, instantiating device under test (DUT), testbenches with self-checking. Simulation only, not synthesizable.

Processor, the architectural view

55. The difference between architecture and microarchitecture
Architecture: Programmer’s view of computer (instruction set, software visible registers)

Microarchitecture: Hardware engineer’s view of computer (pipeline structure, hardware visible registers)

56. Processor architectures: Intel/AMD x86, ARM, MIPS
57. MIPS: Instruction encoding and decoding
57. Arithmetic instructions: addu, addiu, subu, mul
58. Bitwise logical instructions: and, or, xor, nor, andi, ori, xori
59. Shifts: sll, sllv, sra, srav, srl, srlv
60. The difference between arithmetic and logical shifts
61. Using arithmetic shifts for signed division with power of 2 operand
62. Loading constants: synthetic operations li and la, operation lui (load upper immediate)
63. “Set if” operations: slt, slti, sltu, sltiu
64. Loads and stores: lb, lbu, lh, lhu, lw, sb, sh, sw
65. Conditional branches: beq, bgez, bgtz, bne, bltz, blez
67. Absolute branches: j, jr
68. Function/subroutine calls: jal, jalr
69. Concept of stack and stack pointers, storing return address and registers in stack
70. How to translate C construct “if-else” into MIPS assembly language?
71. How to translate C construct “while” loop into MIPS assembly language?
72. How to translate C construct “for” loop into MIPS assembly language?
73. How to translate C function call into MIPS assembly language?
74. The concept of exceptions and interrupts. Changing control during exception.
75. The concept of Instruction set simulator (ISS). MARS simulator as an example

Processor, microarchitectural view

76. Processor performance definitions:

Execution Time = (#instructions) (cycles / instruction) (seconds / cycle)
CPI : Cycles Per Instruction
Clock period: seconds per cycle
Clock frequency: 1 / clock period. Unit: Hz
IPC: Instructions Per Cycle

77. Building single cycle processor:

Program counter
Register file: array of flip-flops and muxes
Memory: viewed as black box: address and output

78. The concept of ALU - Arithmetic and Logic Unit

79. Processing stages in single-cycle processor:

Fetch instruction
Read source operands from register file
Compute memory address using ALU
Memory read
Determine address of next instruction

80. The concept of Control Unit: getting opcode from instruction, generating signals for multiplexors

81. Problem with single-cycle design: critical path is too long. A solution: multi-cycle design.

Adding registers that keep values between clock cyles
Increased clock speed
Use finite state machine in Control Unit to generate multiplexer select and register enables

82. The concept of pipelining.

83. Stages of pipelined MIPS implementation: Fetch, Decode, Execute, Memory, Writeback

84. [The concept of data hazard: when instruction depends on the result of previous instruction]

85. Advanced microarchitecture solutions:

Deep (long) pipelines - limited by frequent pipeline flushes during jumps

Branch prediction - improves performance for deep pipelines

Superscalar - multiple pipelines, limited by instruction dependencies

Out of order - improves superscalar

Vector / SIMD processors - one instruction operates with arrays of data (SIMD = Single Instruction Multiple Data) - requires special programming

Multiprocessors - limited by memory sharing


Memory hierarchy:

86. The concept of addressable memory: address, write data, write enable signal, read data

87. Memory types

Dynamic random access memory - DRAM
Static random access memory - SRAM
Read only memory - ROM

88. Processor-memory gap -> need for caches

89. The concept of cache: exploiting temporal locality and spacial locality

90. The structure of cache: lines (blocks), indices, tags, sets

91. Types of cache: direct-mapped, N-way set associative, fully associative

92. Cache performance measurement: hits and misses; miss rate
93. Cache hierarchy - L1, L2, L3 …

94. Cache coherence for multi-core systems. Snooping protocols (MESI), directory-based protocols.

Practical skills from lab exercises:

95. The structure of a breadboard for experimentation

96. How to choose a resistor for LED

96. The need for pullup and pulldown resistors. How to connect a button to an input into FPGA or MCU

97. The need for button de-bouncing. Methods for debouncing when used with FPGA

98. The definition and structure of Field Programmable Gate Arrays - FPGA (cells, logical elements)

Misc

99. Other SoC components - graphical processors (GPU), video processors (VPU), radio (RPU)

100. Bus protocols for component connectivity:

On-chip buses: AMBA AHB-Lite, AXI, OCP
Off-chip interfaces: SPI, UART, I2C, Ethernet, USB etc

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